1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a semiconductor device which can stabilize and fix an electric potential at a signal input terminal while the latter is not in use.
2. Description of Related Art
A semiconductor-chip device incorporating a CPU (central processing unit) and circuits controlled by the CPU is provided with a signal input terminal (hereinafter "input terminal"). If this input terminal is kept open (the state of high impedance) while it is not used, the potential at this input terminal is likely to become unstable because of external noise, thereby causing the malfunction of the CPU and other devices. In order to prevent this problem and to stabilize the potential at the input terminal, a source voltage or a grounded voltage is applied to the input terminal.
FIG. 1 is a block diagram showing the known semiconductor device. The illustrated semiconductor device A1 is provided with an input terminal 4 which is connected to a d.c. power supply VC through a mask option division 11 of a P-channel transistor PT, serving as a pull-up resistance, whose source S is connected to the gate G of a P-channel transistor PT. The input terminal 4 is connected to an input terminal of an inverter 12. The semiconductor device A1 is fabricated by injecting B (boron) into the mask option division 11 in the wafer process so as to form a charge path and use the P-channel transistor PT as a pull-up resistance.
In the semiconductor device A1, since the d.c. power supply Vc is connected to the gate G of the P-channel transistor PT, the P-channel transistor PT is likely to remain ON, thereby causing the d.c. power supply Vc to continue to apply a d.c. voltage across the input terminal 4. In this way, while the input terminal 4 is not in use, the potential at the input terminal 4 is fixed by the voltage of the d.c. power supply Vc.
FIG. 2 shows a modified version of the known semiconductor device. The illustrated semiconductor device A2 is provided with an input terminal 4 which is connected to the d.c. power supply Vc through P-channel transistor PT, and also to the input terminal of an inverter 12. A signal from a CPU 15 is inputted to a latch circuit 5 whose content is inputted to the gate of a P-channel transistor PT. The latch circuit 5 has a reset terminal grounded through an N-channel transistor NT. A reset signal 8 is inputted to the gate of the N-channel transistor NT.
In this semiconductor device A2, the signal is inputted to the latch circuit 5 from the CPU 15 so as to lower the content of the latch circuit 5 to L-level. Thus the P-channel transistor PT remains ON, thereby applying a voltage of the d.c. power supply Vc to the input terminal 4. In this way, while the input terminal is not in use, the potential at the input terminal 4 is fixed to the voltage of the d.c. power supply Vc. If a reset signal 8 on H-level occurs within the semiconductor device A2, the reset signal 8 turns on the N-channel transistor NT, thereby resetting the latch circuit 5. The content of the latch circuit 5 is raised to H-level, thereby turning off the P-channel transistor PT. Thus the input terminal 4 is disconnected from the d.c. power supply Vc. Later, when a signal is again inputted to the latch circuit 5 from the CPU 15, the content thereof is lowered to L-level, thereby turning on the P-channel transistor PT. In this way, the potential at the input terminal 4 is fixed by the voltage of the d.c. power supply Vc.
In the semiconductor device shown in FIG. 1, when B (boron) is injected into the mask option division, the P-channel transistor remains ON and is not turned off. As a result, after the semiconductor device A1 is manufactured, if there arises a need for using an input terminal not expected to be used by inputting a signal thereto, it is impracticable. In the semiconductor device shown in FIG. 2, the latch circuit is reset each time a reset signal is generated in the CPU, thereby resulting in the unstability of the potential at the input terminal, and the malfunction of the CPU.